vivado参数传递问题

[王阳]

为什么此处 dp_en信号固定成了6’b000001,我在debug模块中无论如何设置dp_en,传递给digital_tubo模块值都是6’b000001.digital_tubo 模块在内部把参数设置好是正确的。代码如下：

module debug(
output [23:0]show_data,

output [5:0] dp_en
);//debug 模块

parameter T = 24’b0001_0100_0010_0011_0101_0110;
parameter P = 6’b110_011;
assign show_data = T;

assign dp_en = P;

endmodule

 

module ad_collaction_debug_top(
input sys_clk_50m,
input sys_rst_n,
input [1:0] SW,

output [5:0] SEAT,
output [7:0] SEG,
output [7:0] LED
);//top模块

wire show_data;

wire dp_en;
//assign show_data = 24’b0001_0100_0010_0011_0101_0110;

//assign dp_en = 6’b110_011;//
debug debug_inst(
.show_data(show_data),

.dp_en(dp_en)
);

digital_tubo digital_tubo_inst(
.sys_clk_50m(sys_clk_50m),
.sys_rst_n(sys_rst_n),

.show_data(show_data),
.dp_en(dp_en),

.SEAT(SEAT),
.SEG(SEG)
);

endmodule

module digital_tubo(
input sys_clk_50m,
input sys_rst_n,

input [23:0] show_data,
input [5:0] dp_en,

output [5:0] SEAT,
output [7:0] SEG
);

reg [25:0] count;
parameter T = 50_000;
reg [23:0] bcd_data_r;
reg [3:0] seg_st;
reg [5:0] sel;
reg [7:0] seg;

wire rst_n;

assign rst_n = sys_rst_n;

assign SEAT = sel;
assign SEG = seg;

always@(posedge sys_clk_50m,negedge rst_n)
begin
if(!rst_n)
count <= 0;
else if(count == T – 1 )
count <= 0;
else
count <= count + 1;
end

always@(posedge sys_clk_50m or negedge rst_n)
if(!rst_n)
sel <= 6’b111_110;
else if(count == T – 1)
begin
sel <= {sel[4:0],sel[5]};
end
else
sel <= sel;

always@(posedge sys_clk_50m,negedge rst_n)//不能再多个always模块里对变量赋值
if(!rst_n)
seg_st <= 0;
else
begin
bcd_data_r <= show_data;
case(sel)
6’b111110: seg_st <= bcd_data_r[3:0];
6’b111101: seg_st <= bcd_data_r[7:4];
6’b111011: seg_st <= bcd_data_r[11:8];
6’b110111: seg_st <= bcd_data_r[15:12];
6’b101111: seg_st <= bcd_data_r[19:16];
6’b011111: seg_st <= bcd_data_r[23:20];
default:seg_st <= 4’b0000;
endcase
end

always@(posedge sys_clk_50m)
if(!rst_n)
seg <= 8’b0100_0000;
else
begin
case(seg_st)
4’b0000: seg[6:0] <= 7’b100_0000;
4’b0001: seg[6:0] <= 7’b111_1001;
4’b0010: seg[6:0] <= 7’b010_0100;
4’b0011: seg[6:0] <= 7’b011_0000;
4’b0100: seg[6:0] <= 7’b001_1001;
4’b0101: seg[6:0] <= 7’b001_0010;
4’b0110: seg[6:0] <= 7’b000_0010;
4’b0111: seg[6:0] <= 7’b111_1000;
4’b1000: seg[6:0] <= 7’b000_0000;
4’b1001: seg[6:0] <= 7’b001_0000;
default: seg[6:0] <= 7’b100_0000;
endcase
case(sel)
6’b111110: seg[7] <=dp_en[0];
6’b111101: seg[7] <=dp_en[1];
6’b111011: seg[7] <=dp_en[2];
6’b110111: seg[7] <=dp_en[3];
6’b101111: seg[7] <=dp_en[4];
6’b011111: seg[7] <=dp_en[5];
default: seg[7] <= 1;
endcase

end

endmodule

[王阳]

我在top模块中赋值的时候给 show_data和dp_en指定位宽就好了。这是根据什么语法规则呢？是不是设计内部的赋值都要指定好位宽才能正确传送？

[tzhuang]

可以采用parameter 传递位宽，参见Verilog 预编译

[201008班_刘璇]

不指定位宽，默认不就是一位嘛

[匿名]

Vivado,参数传递问题

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