vivado 中产生bitstream的时候报错,请问是什么问题

[王阳]

编译数码管显示的程序时Synthesis成功，但是生成bitstream的时候报错。错误信息如下：

[DRC MDRV-1] Multiple Driver Nets: Net seg_st[0] has multiple drivers: seg_st_reg[0]/Q, and seg_st_reg[0]__0/Q.

代码如下：

module seg_driver(
input IN_CLK_50M,
input rst_n,

output reg [7:0] seg,
output reg [5:0] sel
);

parameter T = 50_000_000;

reg [25:0] count;
reg [3:0] seg_st;
reg [3:0] sel_st;

always@(posedge IN_CLK_50M or negedge rst_n)
begin
if(!rst_n)
begin
count <= 0;
sel <=6’b111110;
seg_st <= 4’b0000;
end
else
begin
sel <= 6’b111101;
seg_st <= 4’b0010;
end
end

always@(posedge IN_CLK_50M)
begin
case(seg_st)
4’b0000: seg <= 8’b1100_0000;
4’b0001: seg <= 8’b1111_1001;
4’b0010: seg <= 8’b1010_0100;
4’b0011: seg <= 8’b1011_0000;
4’b0100: seg <= 8’b1001_1001;
4’b0101: seg <= 8’b1001_0010;
4’b0110: seg <= 8’b1000_0010;
4’b0111: seg <= 8’b1111_1000;
4’b1000: seg <= 8’b1000_0000;
4’b1001: seg <= 8’b1001_0000;
default: seg <=8’b0100_0000;
endcase
end

always@(posedge IN_CLK_50M)
begin
case(sel)
6’b111110: seg_st <= 4’b0000;
6’b111101: seg_st <= 4’b0001;
6’b111011: seg_st <= 4’b0010;
6’b110111: seg_st <= 4’b0011;
6’b101111: seg_st <= 4’b0100;
6’b011111: seg_st <= 4’b0101;
default:seg_st <= 0;
endcase
end

endmodule

[王阳]

找到问题所在了，我在2个always块中都对seg_st 赋值，导致寄存器有多个驱动所以报错

[Nikola]

ok

[Nikola]

ok

[Nikola]

ok

[作者]

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