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使用quartus自带modelsim仿真问题

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    • #9893
      201008班_刘璇
      参与者

      仿真报错
      仿真的时候出现这种情况,不知道是什么原因造成的?

      //以下是仿真报错的代码
      # Reading C:/intelFPGA_lite/18.1/modelsim_ase/tcl/vsim/pref.tcl
      # do key_jitter_run_msim_rtl_verilog.do
      # if {[file exists rtl_work]} {
      # vdel -lib rtl_work -all
      # }
      # vlib rtl_work
      # ** Warning: (vlib-14) Failed to open “modelsim.ini” specified by the MODELSIM environment variable.
      # vmap work rtl_work
      # ** Warning: (vmap-14) Failed to open “modelsim.ini” specified by the MODELSIM environment variable.
      # Model Technology ModelSim – Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
      # vmap work rtl_work
      # ** Warning: (vmap-20) Cannot access for reading file “modelsim.ini”.
      # No such file or directory. (errno = ENOENT)
      # ** Error: (vmap-20) Cannot access for writing file “modelsim.ini”.
      # No such file or directory. (errno = ENOENT)
      # Error in macro ./key_jitter_run_msim_rtl_verilog.do line 6
      # ** Warning: (vmap-14) Failed to open “modelsim.ini” specified by the MODELSIM environment variable.
      # Model Technology ModelSim – Intel FPGA Edition vmap 10.5b Lib Mapping Utility 2016.10 Oct 5 2016
      # vmap work rtl_work
      # ** Warning: (vmap-20) Cannot access for reading file “modelsim.ini”.
      # No such file or directory. (errno = ENOENT)
      # ** Error: (vmap-20) Cannot access for writing file “modelsim.ini”.
      # No such file or directory. (errno = ENOENT)
      # while executing
      # “error [FixExecError $msg]”
      # (procedure “vmap” line 29)
      # invoked from within
      # “vmap work rtl_work”

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