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VHDL 关键字


abs     access     after         alias      all         and   architecture   array   assert   attribute
begin    block      body          buffer     bus 
case     component   configuration constant   disconnect downto 
else     elsif       end           entity     exit
file     for         function
generate generic     group         guarded
if       impure      in            inertial   inout      is
label    library     linkage       literal    loop 
map      mod 
nand     new         next          nor        not         null
of       on          open          or         others      out
package  port        postponed     procedural procedure   process protected   pure
range    record      reference     register   reject      rem     report      return
rol      ror 
select   severity    signal        shared     sla         sll     sra         srl      subtype
then     to          transport     type 
unaffected            units         until      use
wait     when        while         with
xnor     xor

由于VHDL语言不却分字母的大小写,因此如下列出的关键字以小写方式给出,但其中的大写,大小写组合也被视为关键字的一个部分,不能再作为一般的标识符使用。如begin为VHDL语言的关键字,则Begin,BIgin, BIGen, BIGEn, BIGEN等都不能再作为普通的标识符使用,否则会引起编译时的语法错误。

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